Workshop on Programming Models for SIMD/Vector ProcessingWPMVP 2019

Call for Papers

SIMD processing is still a main driver of performance in general purpose processor architectures besides multi-core technology. Both technologies increase the potential performance by factors, but have to be be explicitly utilized by the software. To expose those different levels of parallelism in a productive and manageable way is still an active area of research. NVIDIA stirred the programming interface scene with the development of a simple yet efficient performance-oriented application programmer interface. OpenACC, OpenMP 4.0, OpenCL, Cilk+ and icpc are just examples for many choices available. Additionally, established optimizing compilers still improve significantly in unleashing the SIMD potential. Notable developments on the hardware side include relaxation of alignment requirements and more powerful scatter/gather and shuffle instructions. Recent developments include the introduction of 512bit SIMD units in general purpose processors (AVX512) and new innovations as the Scalable Vector Extension for the ARMv8-A architecture or the NEC Aurora TSUBASA vector processors.

Scope

The purpose of this workshop is to bring together practitioners and researchers from academia and industry to discuss issues, solutions, and opportunities in enabling application developers to effectively exploit SIMD/vector processing in modern processors. We seek submissions that cover all aspects of SIMD/vector processing. Topics of interests include, but are not restricted to:

• Programming models for SIMD/vector processing
• C/C++/Fortran extensions for SIMD (e.g., OpenMP, OpenACC, OpenCL, SIMD intrinsics)
• New data parallel or streaming programming models for SIMD
• Exploitation of SIMD/vector in Java, scripting languages, and domain-specific languages
• Compilers & tools to discover and optimize SIMD parallelism
• Case study, experience report, and performance analysis of SIMD/vector applications
• Design of algorithms specially suited to SIMD/vector architecture

Submission Link

Submitted papers must be no more than 8 pages in length. Authors are encouraged to use the ACM two-column format here. Each submission on easychair will receive at least three reviews from the technical program committee. The workshop uses double-blind review, which means that author identities are concealed.

Authors must register and submit the paper through online submission system, if you have problems accessing the system, e-mail your submission to wpmvp@lip6.fr.

Keynotes

two keynotes have been confirmed:

• Erich Focht (NEC): Vector Computer Evolution
• Francesco Petrogalli (ARM): SVE programming models

bio’s and abstracts coming soon

Organisers:

• Jan Eitzinger (RRZE, University Erlangen-Nuremberg, Germany)
• Sylvain Jubertie (LIFO, University of Orleans, France)
• Lionel Lacassagne (LIP6, Sorbonne University, France)
• Bertrand Le Gal (IMS Lab, Institut Polytechnique of Bordeaux, France)

Accepted Papers