PPoPP 2019
Sat 16 - Wed 20 February 2019 Washington, DC, United States
Mon 18 Feb 2019 14:50 - 15:15 at Salon 12/13 - Session 3: Transactional Memory Chair(s): Milind Chabbi

The hardware transactional memory (HTM) implementations in commercially available processors are significantly hindered by their tight capacity constraints. In practice, this renders current HTMs unsuitable to many real-world workloads of in-memory databases. This paper proposes SI-HTM, which stretches the capacity bounds of the underlying HTM, thus opening HTM to a much broader class of applications. SI-HTM leverages the HTM implementation of the IBM POWER architecture with a software layer to offer a single-version implementation of Snapshot Isolation. When compared to HTM- and software-based concurrency control alternatives, SI-HTM exhibits improved scalability, achieving speedups of up to 300% relatively to HTM on in-memory database benchmarks.

Mon 18 Feb

14:00 - 15:40: Main Conference - Session 3: Transactional Memory at Salon 12/13
Chair(s): Milind ChabbiUber Technologies
PPoPP-2019-papers14:00 - 14:25
Brijesh DongolUniversity of Surrey, Radha JagadeesanDePaul University, James RielyDePaul University
PPoPP-2019-papers14:25 - 14:50
Ryan Yates, Michael ScottUniversity of Rochester
DOI Authorizer link File Attached
PPoPP-2019-papers14:50 - 15:15
Ricardo Jorge Duarte Filipe, Shady IssaINESC-ID, João BarretoINESC-ID, Paolo RomanoUniversity of Lisbon, Portugal
PPoPP-2019-papers15:15 - 15:40
Mohamed M. SaadVirginia Tech, Masoomeh Javidi KishiLehigh University, Shihao JingLehigh University, Sandeep HansIBM India Research Lab, Roberto PalmieriLehigh University